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SM59R16A2 Datasheet(PDF) 21 Page - SyncMOS Technologies,Inc |
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SM59R16A2 Datasheet(HTML) 21 Page - SyncMOS Technologies,Inc |
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21 / 67 page  SM59R16A2/SM59R08A2 8-Bit Micro-controller 64KB/32KB ISP Flash & 2KB RAM embedded Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 21 Ver.B SM59R16A2/SM59R08A2 06/2009 4.6 Data Pointer 1 The dual data pointer accelerates the moving of block data. The standard DPTR is a 16-bit register that is used to address external memory or peripherals. In the SM59R16A2/SM59R08A2, the standard data pointer is called DPTR, the second data pointer is called DPTR1. The data pointer select bit chooses the active pointer. The data pointer select bit is located in the LSB of DPS register (DPS.0). The user switches the pointer between PDTR and DPTR1 by toggling the LSB of DPS register. All DPTR-related instructions use the currently selected DPTR for any activity. Mnemonic: DPL1 Address: 84h 7 6 5 4 3 2 1 0 Reset DPL1 [7:0] 00h DPL1[7:0]: Data pointer Low 1 Mnemonic: DPH1 Address: 85h 7 6 5 4 3 2 1 0 Reset DPH1 [7:0] 00h DPH1[7:0]: Data pointer High 1 Mnemonic: DPS Address: 92h 7 6 5 4 3 2 1 0 Reset - - - - - - - DPS.0 00h DPS.0: Data Pointer selects register. DPS.0 = 1 is selected DPTR1. 4.7 Interface control register Mnemonic: IFCON Address: 8Fh 7 6 5 4 3 2 1 0 Reset ITS - - - ALEC[1:0] DMEN - 00h ITS: Instruction timing select. ITS = 0, 2T instruction mode. ITS = 1, 1T instruction mode. ALEC[1:0]: ALE output control register. ALEC[1:0] ALE Output 00 Always output 01 No ALE output 10 Only Read or Write have ALE output 11 reserved DMEN: Internal 2K SRAM disable.(default is enable) DMEN = 0, Enable internal 2K RAM. DMEN = 1, Disable internal 2K RAM. |
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