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SM59R16A2 Datasheet(PDF) 23 Page - SyncMOS Technologies,Inc |
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SM59R16A2 Datasheet(HTML) 23 Page - SyncMOS Technologies,Inc |
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23 / 67 page  SM59R16A2/SM59R08A2 8-Bit Micro-controller 64KB/32KB ISP Flash & 2KB RAM embedded Specifications subject to change without notice contact your sales representatives for the most recent information. ISSFD-M034 23 Ver.B SM59R16A2/SM59R08A2 06/2009 6 Multiplication Division Unit (MDU) This on-chip arithmetic unit provides 32-bit division, 16-bit multiplication, shift and normalize features, etc. All operations are unsigned integer operations. Mnemonic Description Direct Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET Multiplication Division Unit PCON Power control 87h SMOD MDUF - PMW - - STOP IDLE 00h ARCON Arithmetic Control register EFh MDEF MDOV SLR SC [4:0] 00h MD0 Multiplication/Div ision Register 0 E9h MD0 [7:0] 00h MD1 Multiplication/Div ision Register 1 EAh MD1 [7:0] 00h MD2 Multiplication/Div ision Register 2 EBh MD2 [7:0] 00h MD3 Multiplication/Div ision Register 3 ECh MD3 [7:0] 00h MD4 Multiplication/Div ision Register 4 EDh MD4 [7:0] 00h MD5 Multiplication/Div ision Register 5 EEh MD5 [7:0] 00h 6.1 Operation of the MDU The operation of the MDU consists of three phases: 6.1.1 First phase: loading the MDx registers, x = 0~5: The type of calculation the MDU has to perform is selected by the order in which the MDx registers are written to. A write to MD0 is the first transfer to be done in any case. Next writes must be done as shown in table below to determine MDU operation. The last write will start the selected operation. Table 6-1: MDU registers write sequence Operation 32bit/16bit 16bit/16bit 16bit x 16bit shift/normalizing First write MD0 Dividend Low MD0 Dividend Low MD0 Multiplicand Low MD0 LSB MD1 Dividend MD1 Dividend High MD4 Multiplicator Low MD1 MD2 Dividend MD1 Multiplicand High MD2 MD3 Dividend High MD3 MSB MD4 Divisor Low MD4 Divisor Low Last write MD5 Divisor High MD5 Divisor High MD5 Multiplicator High ARCON start conversion |
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