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AT91RM9200-CJ-002 Datasheet(PDF) 67 Page - ATMEL Corporation |
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AT91RM9200-CJ-002 Datasheet(HTML) 67 Page - ATMEL Corporation |
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67 / 701 page  67 1768I–ATARM–09-Jul-09 AT91RM9200 12.6.4.3 Application Board Restriction The TCLK signal needs to be set with care, some timing parameters are required. Refer to AT91RM9200 “JTAG/ICE Timings” on page 657 and “ETM Timings” on page 660. The specified target system connector is the AMP Mictor connector. The connector must be oriented on the application board as described below in Figure 12-6. The view of the PCB is shown from above with the trace connector mounted near the edge of the board. This allows the Trace Port Analyzer to minimize the physical intrusiveness of the inter- connected target. Figure 12-6. AMP Mictor Connector Orientation 12.6.5 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be per- formed (NRST and NTRST) after JTAGSEL is changed. Two Boundary Scan Descriptor Language (BSDL) files are provided to set up testing. Each BSDL file is dedicated to a specific packaging. 12.6.5.1 JTAG Boundary Scan Register The Boundary Scan Register (BSR) contains 449 bits which correspond to active pins and asso- ciated control signals. Each AT91RM9200 input pin has a corresponding bit in the Boundary Scan Register for observability. Each AT91RM9200 output pin has a corresponding 2-bit register in the BSR. The OUTPUT bit contains data which can be forced on the pad. The CTRL bit can put the pad into high impedance. 38 37 2 1 Pin 1Chamfer AT91RM9200-based Application Board |
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