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AT91RM9200-CJ-002 Datasheet(PDF) 37 Page - ATMEL Corporation |
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AT91RM9200-CJ-002 Datasheet(HTML) 37 Page - ATMEL Corporation |
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37 / 701 page  37 1768I–ATARM–09-Jul-09 AT91RM9200 Registers R0 to R7 are unbanked registers, thus each of them refers to the same 32-bit physical register in all processor modes. They are general-purpose registers, with no special uses man- aged by the architecture, and can be used wherever an instruction allows a general-purpose register to be specified. Registers R8 to R14 are banked registers. This means that each of them depends of the current processor mode. For further details, see the ARM Architecture Reference Manual, Rev. DDI0100E. 11.3.4.1 Modes and Exception Handling All exceptions have banked registers for R14 and R13. After an exception, R14 holds the return address for exception processing. This address is used both to return after the exception is processed and to address the instruction that caused the exception. R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin with- out the need to save these registers. R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R8 R8 R8 R8 R8 R8_FIQ R9 R9 R9 R9 R9 R9_FIQ R10 R10 R10 R10 R10 R10_FIQ R11 R11 R11 R11 R11 R11_FIQ R12 R12 R12 R12 R12 R12_FIQ R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ PC PC PC PC PC PC CPSR CPSR CPSR CPSR CPSR CPSR SPSR_SVC SPSR_ABO RT SPSR_UND EF SPSR_IRQ SPSR_FIQ Mode-specific banked registers Table 11-1. ARM9TDMI Modes and Register Layout (Continued) User and System Mode Supervisor Mode Abort Mode Undefined Mode Interrupt Mode Fast Interrupt Mode |
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