ATmega165 datasheet(207/336 Pages) ATMEL

207 / 336 page

207

ATmega165/V

2573G–AVR–07/09

The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT –

which is not provided.

When the JTAGEN fuse is unprogrammed, these four TAP pins are normal port pins

and the TAP controller is in reset. When programmed and the JTD bit in MCUCSR is

cleared, the TAP pins are internally pulled high and the JTAG is enabled for Boundary-

scan and programming. The device is shipped with this fuse programmed.

For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is

monitored by the debugger to be able to detect external reset sources. The debugger

can also pull the RESET pin low to reset the whole system, assuming only open collec-

tors on the reset line are used in the application.

Figure 97. Block Diagram

TAP

CONTROLLER

TDI

TDO

TCK

TMS

FLASH

MEMORY

AVR CPU

DIGITAL

PERIPHERAL

UNITS

JTAG / AVR CORE

COMMUNICATION

INTERFACE

BREAKPOINT

UNIT

FLOW CONTROL

UNIT

OCD STATUS

AND CONTROL

INTERNAL

SCAN

CHAIN

INSTRUCTION

BYPASS

JTAG PROGRAMMING

INTERFACE

Instruction

Address

Data

BREAKPOINT

SCAN CHAIN

ADDRESS

DECODER

ANALOG

PERIPHERIAL

UNITS

I/O PORT 0

I/O PORT n

BOUNDARY SCAN CHAIN

Analog inputs

Control & Clock lines

DEVICE BOUNDARY

ATmega165 Datasheet(PDF) 207 Page - ATMEL Corporation

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