ATmega165 datasheet(261/336 Pages) ATMEL

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261

ATmega165/V

2573G–AVR–07/09

Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI

bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI

(input) and MISO (output). After RESET is set low, the Programming Enable instruction

needs to be executed first before program/erase operations can be executed. NOTE, in

Table 111 on page 251, the pin mapping for SPI programming is listed. Not all parts use

the SPI pins dedicated for the internal SPI interface.

Figure 120. Serial Programming and Verify(1)

Notes:1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to

the XTAL1 pin.

CC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 - 5.5V

When programming the EEPROM, an auto-erase cycle is built into the self-timed pro-

gramming operation (in the Serial mode ONLY) and there is no need to first execute the

Chip Erase instruction. The Chip Erase operation turns the content of every memory

location in both the Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high

periods for the serial clock (SCK) input are defined as follows:

Low:> 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

High:> 2 CPU clock cycles for f

ck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

VCC

GND

XTAL1

SCK

MISO

MOSI

RESET

+1.8 - 5.5V

AVCC

+1.8 - 5.5V

(2)

ATmega165 Datasheet(PDF) 261 Page - ATMEL Corporation