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ATtiny167 Datasheet(PDF) 106 Page - ATMEL Corporation |
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ATtiny167 Datasheet(HTML) 106 Page - ATMEL Corporation |
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106 / 282 page  106 7728D–AVR–07/09 ATtiny87/ATtiny167 10.11.7 General Timer/Counter Control Register – GTCCR • Bit 1 – PSR0: Prescaler Reset Timer/Counter0 When this bit is one, the Timer/Counter0 prescaler will be reset. This bit is normally cleared immediately by hardware. If the bit is written when Timer/Counter0 is operating in asynchro- nous mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Synchronization Mode” on page 109 for a description of the Timer/Counter Synchronization mode. Bit 7 6 5 4 3 2 1 0 TSM – – – – – PSR0 PSR1 GTCCR Read/Write R/W R R R R R R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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