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ATtiny167 Datasheet(PDF) 208 Page - ATMEL Corporation |
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ATtiny167 Datasheet(HTML) 208 Page - ATMEL Corporation |
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208 / 282 page ![]() 208 7728D–AVR–07/09 ATtiny87/ATtiny167 17.11.3 ADCL and ADCH – The ADC Data Register 17.11.3.1 ADLAR = 0 17.11.3.2 ADLAR = 1 When an ADC conversion is complete, the result is found in these two registers. When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH. Otherwise, ADCL must be read first, then ADCH. The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result is right adjusted. • ADC9:0: ADC Conversion Result These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on page 202. 100 16 101 32 110 64 111 128 Table 17-6. ADC Prescaler Selections (Continued) ADPS2 ADPS1 ADPS0 Division Factor Bit 151413 1211 10 9 8 – – – – – – ADC9 ADC8 ADCH ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL 765 43 21 0 Read/Write RR RR RR RR RR RR RR RR Initial Value 0 0 0 0 0 0 0 0 000 00 00 0 Bit 151413 1211 10 9 8 ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH ADC1 ADC0 – – – – – – ADCL 765 43 21 0 Read/Write RR RR RR RR RR RR RR RR Initial Value 0 0 0 0 0 0 0 0 000 00 00 0 |
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