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ATmega328P Datasheet(PDF) 103 Page - ATMEL Corporation |
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ATmega328P Datasheet(HTML) 103 Page - ATMEL Corporation |
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103 / 345 page ![]() 103 7810A–AVR–11/09 ATmega328P [Preliminary] • Bit 0 – TOV0: Timer/Counter0 Overflow Flag The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 14-8, “Waveform Generation Mode Bit Description” on page 99. |
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