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ATmega16A Datasheet(PDF) 144 Page - ATMEL Corporation |
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ATmega16A Datasheet(HTML) 144 Page - ATMEL Corporation |
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144 / 352 page ![]() 144 8154B–AVR–07/09 ATmega16A • Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock frequency f osc is shown in the following table: 18.5.2 SPSR – SPI Status Register • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR). • Bit 6 – WCOL: Write COLlision Flag The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register. • Bit 5:1 – Res: Reserved Bits These bits are reserved bits in the ATmega16A and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 18-5). This means that the minimum SCK period will be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at f osc/4 or lower. The SPI interface on the ATmega16A is also used for program memory and EEPROM down- loading or uploading. See page 276 for SPI Serial Programming and Verification. Table 18-5. Relationship Between SCK and the Oscillator Frequency SPI2X SPR1 SPR0 SCK Frequency 00 0 f osc/4 00 1 f osc/16 01 0 f osc/64 01 1 f osc/128 10 0 f osc/2 10 1 f osc/8 11 0 f osc/32 11 1 f osc/64 Bit 765 432 10 SPIF WCOL – – – – – SPI2X SPSR Read/Write RR RRR RR R/W Initial Value 0 0 0 0 0 0 0 0 |
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