HT68F20 datasheet(113/210 Pages) HOLTEK

113 / 210 page

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

Rev.1.00

113

November 3, 2009

As the name of the mode suggests, after a comparison

is made, the TM output pin, will change state. The TM

output pin condition however only changes state when

an TnAF or TnBF interrupt request flag is generated af-

ter a compare match occurs from Comparator A or Com-

parator B. The TnPF interrupt request flag, generated

from a compare match from Comparator P, will have no

effect on the TM output pin. The way in which the TM

output pin changes state is determined by the condition

of the TnAIO1 and TnAIO0 bits in the TMnC1 register for

ETM CCRA, and the TnBIO1 and TnBIO0 bits in the

TMnC2 register for ETM CCRB. The TM output pin can

be selected using the TnAIO1, TnAIO0 bits (for the

TPnA pin) and TnBIO1, TnBIO0 bits (for the TPnB_0,

TPnB_1 or TPnB_2 pins) to go high, to go low or to tog-

gle from its present condition when a compare match

occurs from Comparator A or a compare match occurs

from Comparator B. The initial condition of the TM out-

put pin, which is setup after the TnON bit changes from

low to high, is setup using the TnAOC or TnBOC bit for

TPnA or TPnB_0, TPnB_1, TPnB_2 output pins. Note

that if the TnAIO1,TnAIO0 and TnBIO1, TnBIO0 bits are

zero then no pin change will take place.

CCRA

CCRP

0x3FF

Counter

Value

Counter

overflow

CCRA Int.

Flag TnAF

CCRP Int.

Flag TnPF

CCRP > 0

Counter cleared by CCRP value

TPnA O/P Pin

TnON bit

Pause

Count er

Reset

Output Pin

Reset to initial value

Output Pin set

to Initial Level

Low if TnAOC = 0

Output Toggle

with TnAF flag

Here TnAIO1, TnAIO0 = 11

Toggle Output Select

Now TnAIO 1, TnAIO 0 = 10

Act ive High Output Select

Output not af fect ed by TnAF flag

Remains High until reset by TnON bit

TnCCLR = 0; TnAM1, TnAM0 = 00

TnPAU bit

Resume

Stop

Time

CCRP > 0

CCRP = 0

TnAPOL bit

Output inverts

when TnAPOL is high

ETM CCRA Compare Match Output Mode

- TnCCLR = 0

Note:

1. With TnCCLR = 0 the Comparator P match will clear the counter

2. TPnA output pin controlled only by TnAF flag

3. Output pin reset to initial state by TnON bit rising edge

HT68F20 Datasheet(PDF) 113 Page - Holtek Semiconductor Inc

HT68F20 Datasheet(HTML) 113 Page - Holtek Semiconductor Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL