Rev. 0.8 / Oct. 2007

19

For purposes of IDD testing, the following parameters are to be utilized

Detailed IDD7

The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the

specification.

Legend: A = Active; RA = Read with Autoprecharge; D = Deselect

IDD7: Operating Current: All Bank Interleave Read operation

All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) using a burst length of 4. Control

and address bus inputs are STABLE during DESELECTs. IOUT = 0mA

Timing Patterns for 4 bank devices x4/ x8/ x16

-DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)

-DDR2-533 3/3/3: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)

-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D (16 clocks)

-DDR2-667 4/4/4: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)

-DDR2-667 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)

-DDR2-800 5/5/5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D (23 clocks)

-DDR2-800 6/6/6: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D D (24 clocks)

Speed Bin

(CL-tRCD-tRP)

DDR2-800

DDR2-667

DDR2-533

DDR2-400

Units

5-5-5

6-6-6

5-5-5

4-4-4

3-3-3

CL(IDD)

5

6

5

4

3

tCK

tRCD(IDD)

12.5

15

15

15

15

ns

tRC(IDD)

57.25

60

60

60

55

ns

tRRD(IDD)-x4/x8

7.5

7.5

7.5

7.5

7.5

ns

tRRD(IDD)-x16

10

10

10

10

10

ns

tCK(IDD)

2.5

2.5

3

3.75

5

ns

tRASmin(IDD)

45

45

45

45

40

ns

tRASmax(IDD)

70000

70000

70000

70000

70000

ns

tRP(IDD)

12.5

15

15

15

15

ns

tRFC(IDD)-256Mb

75

75

75

75

75

ns

tRFC(IDD)-512Mb

105

105

105

105

105

ns

tRFC(IDD)-1Gb

127.5

127.5

127.5

127.5

127.5

ns