Rev. 0.8 / Oct. 2007

4

1. Description

1.1 Device Features & Ordering Information

1.1.1 Key Features

• VDD ,VDDQ =1.8 +/- 0.1V

• All inputs and outputs are compatible with SSTL_18 interface

• Fully differential clock inputs (CK, /CK) operation

• Double data rate interface

• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)

• Differential Data Strobe (DQS, DQS)

• Data outputs on DQS, DQS edges when read (edged DQ)

• Data inputs on DQS centers when write(centered DQ)

• On chip DLL align DQ, DQS and DQS transition with CK transition

• DM mask write data-in at the both rising and falling edges of the data strobe

• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock

• Programmable CAS latency 3, 4, 5 and 6 supported

• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported

• Programmable burst length 4 / 8 with both nibble sequential and interleave mode

• Internal four bank operations with single pulsed RAS

• Auto refresh and self refresh supported

• tRAS lockout supported

• 8K refresh cycles /64ms

• JEDEC standard 60ball FBGA(x4/x8) & 84ball FBGA(x16)

• Full strength driver option controlled by EMRS

• On Die Termination supported

• Off Chip Driver Impedance Adjustment supported

• Read Data Strobe supported (x8 only)

• Self-Refresh High Temperature Entry

• Partial Array Self Refresh support

Ordering Information

Part No.

Organization

Package

HY5PS12421C(L)FP-X*

128Mx4

Lead free**

HY5PS12821C(L)FP-X*

64Mx8

HY5PS121621C(L)FP-X*

32Mx16

Note:

1. -X* is the speed bin, refer to the Operation Frequency table for

complete Part No.

2. Hynix Lead-free products are compliant to RoHS.

Operating Frequency

Speed Bin tCK(ns)

CL

tRCD tRP

Unit

E3

53

3

3

Clk

C4

3.75

4

4

4

Clk

Y5

35

5

5

Clk

S5

2.5

5

5

5

Clk

S6

2.5

6

6

6

Clk