PIC24F16KA102 datasheet(112/254 Pages) MICROCHIP

112 / 254 page

PIC24F16KA102 FAMILY

DS39927B-page 110

Preliminary

11.1.1

OPEN-DRAIN CONFIGURATION

In addition to the PORT, LAT and TRIS registers for

data control, each port pin can also be individually

configured for either digital or open-drain output. This is

controlled by the Open-Drain Control register, ODCx,

associated with each port. Setting any of the bits

configures the corresponding pin to act as an

open-drain output.

The maximum open-drain voltage allowed is the same

as the maximum VIH specification.

11.2

Configuring Analog Port Pins

The use of the AD1PCFG and TRIS registers control

the operation of the A/D port pins. The port pins that are

desired

analog

inputs

must

have

their

corresponding TRIS bit set (input). If the TRIS bit is

cleared (output), the digital output level (VOH or VOL)

will be converted.

When reading the PORT register, all pins configured as

analog input channels will read as cleared (a low level).

Analog levels on any pin that is defined as a digital

input (including the ANx pins) may cause the input

buffer to consume current that exceeds the device

specifications.

11.2.1

I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically, this instruction

would be a NOP.

11.3

Input Change Notification

The input change notification function of the I/O ports

allows the PIC24F16KA102 family of devices to

generate interrupt requests to the processor in

response to a change of state on selected input pins.

This feature is capable of detecting input change of

states even in Sleep mode, when the clocks are

disabled. Depending on the device pin count, there are

up to 23 external signals (CN0 through CN22) that may

be selected (enabled) for generating an interrupt

request on a change of state.

There are six control registers associated with the CN

module. The CNEN1 and CNEN2 registers contain the

interrupt enable control bits for each of the CN input

pins. Setting any of these bits enables a CN interrupt

for the corresponding pins.

Each CN pin also has a weak pull-up/pull-down

connected to it. The pull-ups act as a current source

that is connected to the pin and the pull-downs act as a

current sink to eliminate the need for external resistors

when push button or keypad devices are connected.

On any pin, only the pull-up resistor or the pull-down

resistor should be enabled, but not both of them. If the

push button or the keypad is connected to VDD, enable

the pull-down, or if they are connected to VSS, enable

the pull-up resistors. The pull-ups are enabled

separately using the CNPU1 and CNPU2 registers,

which contain the control bits for each of the CN pins.

Setting any of the control bits enables the weak

pull-ups for the corresponding pins. The pull-downs are

enabled separately using the CNPD1 and CNPD2

registers, which contain the control bits for each of the

CN pins. Setting any of the control bits enables the

weak pull-downs for the corresponding pins.

When the internal pull-up is selected, the pin uses VDD

as the pull-up source voltage. When the internal

pull-down is selected, the pins are pulled down to VSS

by an internal resistor. Make sure that there is no

external pull-up source/pull-down sink when the

internal pull-ups/pull-downs are enabled.

EXAMPLE 11-1:

PORT WRITE/READ EXAMPLE

Note:

Pull-ups and pull-downs on change

notification

pins

should

always

disabled whenever the port pin is

configured as a digital output.

MOV

0xFF00, W0;

//Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs

MOV

W0, TRISBB;

NOP;

//Delay 1 cycle

BTSS

PORTB, #13;

//Next Instruction

Equivalent ‘C’ Code

TRISB = 0xFF00;

//Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs

NOP();

//Delay 1 cycle

if(PORTBbits.RB13 == 1)

// execute following code if PORTB pin 13 is set.

{

}

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