PIC16F1934-ESLASHML datasheet(101/418 Pages) MICROCHIP

101 / 418 page

Preliminary

DS41364A-page 99

PIC16F193X/LF193X

6.6

PORTE and TRISE Registers

PORTE(1) is a 4-bit wide, bidirectional port. The

corresponding data direction register is TRISE. Setting a

TRISE bit (= 1) will make the corresponding PORTE pin

an input (i.e., put the corresponding output driver in a

High-Impedance mode). Clearing a TRISE bit (= 0) will

make the corresponding PORTE pin an output (i.e.,

enable the output driver and put the contents of the

output latch on the selected pin). The exception is RE3,

which is input only and its TRIS bit will always read as

‘1’. Example 6-5 shows how to initialize PORTE.

Reading the PORTE register (Register 6-18) reads the

status of the pins, whereas writing to it will write to the

PORT latch. All write operations are read-modify-write

operations. Therefore, a write to a port implies that the

port pins are read, this value is modified and then

written to the PORT data latch. RE3 reads ‘0’ when

MCLRE = 1.

EXAMPLE 6-5:

INITIALIZING PORTE

Note 1: RE<2:0>

and

TRISE<2:0>

pins

are

available

PIC16F1936

and

PIC16F1938 only.

BANKSEL PORTE

;

CLRF

PORTE

;Init PORTE

BANKSEL ANSELE

;

CLRF

ANSELE

;digital I/O

BANKSEL TRISE

;

MOVLW

B‘00001100’

;Set RE<3:2> as inputs

MOVWF

TRISE

;and set RE<1:0>

;as outputs

PORTE: PORTE REGISTER

U-0

R-x/u

R/W-x/u

—

RE3

RE2(1)

RE1(1)

RE0(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-4

Unimplemented: Read as ‘0’

bit 3-0

RE<3:0>: PORTE I/O Pin bits(1)

= Port pin is > VIH

= Port pin is < VIL

Note 1:

RE<2:0> are not implemented on the PIC16F1933/1936/1938. Read as ‘0’.

LATE: PORTE DATA LATCH REGISTER

U-0

R/W-x/u

—

LATE3

LATE2

LATE1

LATE0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7-4

Unimplemented: Read as ‘0’

bit 3-0

LATE<3:0>: PORTE Output Latch Value bits(1)

Note 1:

Writes to PORTE are actually written to corresponding LATE register. Reads from PORTE register is

return of actual I/O pin values.

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