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dsPIC30F2012 Datasheet(PDF) 200 Page - Microchip Technology |
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dsPIC30F2012 Datasheet(HTML) 200 Page - Microchip Technology |
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200 / 206 page  dsPIC30F2011/2012/3012/3013 DS70139F-page 200 © 2008 Microchip Technology Inc. Power-on Reset (POR) ............................................. 121 Power-up Timer (PWRT) .......................................... 121 Reset Sequence.................................................................. 67 Reset Sources ............................................................ 67 Reset Sources Brown-out Reset (BOR) .............................................. 67 Illegal Instruction Trap................................................. 67 Trap Lockout ............................................................... 67 Uninitialized W Register Trap ..................................... 67 Watchdog Time-out..................................................... 67 Reset Timing Characteristics ............................................ 163 Reset Timing Requirements.............................................. 163 Run-Time Self-Programming (RTSP) ................................. 49 S Simple Capture Event Mode ............................................... 83 Buffer Operation.......................................................... 84 Hall Sensor Mode ....................................................... 84 Prescaler..................................................................... 83 Timer2 and Timer3 Selection Mode............................ 84 Simple OC/PWM Mode Timing Requirements.................. 169 Simple Output Compare Match Mode................................. 88 Simple PWM Mode ............................................................. 88 Input Pin Fault Protection............................................ 88 Period.......................................................................... 89 Software Simulator (MPLAB SIM)..................................... 144 Software Stack Pointer, Frame Pointer............................... 20 CALL Stack Frame...................................................... 39 SPI Module.......................................................................... 91 Framed SPI Support ................................................... 92 Operating Function Description .................................. 91 Operation During CPU Idle Mode ............................... 93 Operation During CPU Sleep Mode............................ 93 SDOx Disable ............................................................. 92 Slave Select Synchronization ..................................... 93 SPI1 Register Map...................................................... 94 Timing Characteristics Master Mode (CKE = 0) .................................... 170 Master Mode (CKE = 1) .................................... 171 Slave Mode (CKE = 1) .............................. 172, 173 Timing Requirements Master Mode (CKE = 0) .................................... 170 Master Mode (CKE = 1) .................................... 171 Slave Mode (CKE = 0) ...................................... 172 Slave Mode (CKE = 1) ...................................... 174 Word and Byte Communication .................................. 92 Status Bits, Their Significance and the Initialization Condition for RCON Register, Case 1 ...................... 130 Status Bits, Their Significance and the Initialization Condition for RCON Register, Case 2 ...................... 130 Status Register.................................................................... 20 Symbols Used in Opcode Descriptions............................. 136 System Integration Register Map............................................................. 134 T Table Instruction Operation Summary ................................ 49 Temperature and Voltage Specifications AC ............................................................................. 157 DC............................................................................. 147 Timer 2/3 Module ................................................................ 77 Timer1 Module .................................................................... 73 16-bit Asynchronous Counter Mode ........................... 73 16-bit Synchronous Counter Mode ............................. 73 16-bit Timer Mode....................................................... 73 Gate Operation ........................................................... 74 Interrupt ...................................................................... 74 Operation During Sleep Mode .................................... 74 Prescaler .................................................................... 74 Real-Time Clock ......................................................... 74 Interrupts ............................................................ 75 Oscillator Operation............................................ 75 Register Map .............................................................. 76 Timer2 and Timer3 Selection Mode.................................... 88 Timer2/3 Module 16-bit Timer Mode....................................................... 77 32-bit Synchronous Counter Mode ............................. 77 32-bit Timer Mode....................................................... 77 ADC Event Trigger...................................................... 80 Gate Operation ........................................................... 80 Interrupt ...................................................................... 80 Operation During Sleep Mode .................................... 80 Register Map .............................................................. 81 Timer Prescaler .......................................................... 80 Timing Characteristics A/D Conversion Low-speed (ASAM = 0, SSRC = 000) .............. 182 Bandgap Start-up Time............................................. 164 CAN Module I/O........................................................ 179 CLKOUT and I/O ...................................................... 162 External Clock........................................................... 157 I2C Bus Data Master Mode..................................................... 175 Slave Mode....................................................... 177 I2C Bus Start/Stop Bits Master Mode..................................................... 175 Slave Mode....................................................... 177 Input Capture (CAPX)............................................... 167 OC/PWM Module...................................................... 169 Oscillator Start-up Timer........................................... 163 Output Compare Module .......................................... 168 Power-up Timer ........................................................ 163 Reset ........................................................................ 163 SPI Module Master Mode (CKE = 0).................................... 170 Master Mode (CKE = 1).................................... 171 Slave Mode (CKE = 0)...................................... 172 Slave Mode (CKE = 1)...................................... 173 Type A, B and C Timer External Clock ..................... 165 Watchdog Timer ....................................................... 163 Timing Diagrams PWM Output Timing ................................................... 89 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 ..................... 128 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2 ..................... 128 Time-out Sequence on Power-up (MCLR Tied to VDD) ......................................... 128 Timing Diagrams and Specifications DC Characteristics - Internal RC Accuracy............... 160 Timing Diagrams.See Timing Characteristics Timing Requirements A/D Conversion Low-speed ........................................................ 183 Bandgap Start-up Time............................................. 164 Brown-out Reset ....................................................... 163 CAN Module I/O........................................................ 179 CLKOUT and I/O ...................................................... 162 External Clock........................................................... 158 I2C Bus Data (Master Mode) .................................... 176 I2C Bus Data (Slave Mode) ...................................... 177 |
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