PC312XDP512F0CFVR datasheet(208/1348 Pages) FREESCALE

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Chapter 6 XGATE (S12XGATEV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

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3. Tagged Breakpoints

The S12X_DBG module is able to place tags on fetched opcodes. The XGATE is able to enter

debug mode right before a tagged opcode is executed (see section 4.9 of the S12X_DBG Section).

Upon entering debug mode, the program counter will point to the tagged instruction. The other

RISC core registers will hold the result of the previous instruction.

4. Forced Breakpoints

Forced breakpoints are triggered by the S12X_DBG module (see section 4.9 of the S12X_DBG

Section). When a forced breakpoint occurs, the XGATE will enter debug mode upon completion

of the current instruction.

6.6.3

Leaving Debug Mode

Debug mode can only be left by setting the XGDBG bit to "0". If a thread is active (XGCHID has not been

cleared in debug mode), program execution will resume at the value of XGPC.

6.7

Security

In order to protect XGATE application code on secured S12X devices, a few restrictions in the debug

features have been made. These are:

•

Registers XGCCR, XGPC, and XGR1–XGR7 will read zero on a secured device

•

Registers XGCCR, XGPC, and XGR1–XGR7 can not be written on a secured device

•

Single stepping is not possible on a secured device

6.8

Instruction Set

6.8.1

Addressing Modes

For the ease of implementation the architecture is a strict Load/Store RISC machine, which means all

operations must have one of the eight general purpose registers R0 … R7 as their source as well their

destination.

All word accesses must work with a word aligned address, that is A[0] = 0!

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