PC312XDP512F0CFVR datasheet(334/1348 Pages) FREESCALE

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Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

334

Freescale Semiconductor

7.3.2.16

Pulse Accumulator A Flag Register (PAFLG)

Read: Anytime

Write used in the ﬂag clearing mechanism. Writing a one to the ﬂag clears the ﬂag. Writing a zero will not

affect the current status of the bit.

NOTE

When TFFCA = 1, the ﬂags cannot be cleared via the normal ﬂag clearing

mechanism (writing a one to the ﬂag). Reference Section 7.3.2.6, “Timer

System Control Register 1 (TSCR1)”.

All bits reset to zero.

PAFLG indicates when interrupt conditions have occurred. The ﬂags can be cleared via the normal ﬂag

clearing mechanism (writing a one to the ﬂag) or via the fast ﬂag clearing mechanism (Reference TFFCA

bit in Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”).

7.3.2.17

Pulse Accumulators Count Registers (PACN3 and PACN2)

76543210

000000

PAOVF

PAIF

Reset

00000000

= Unimplemented or Reserved

Figure 7-36. Pulse Accumulator A Flag Register (PAFLG)

Table 7-21. PAFLG Field Descriptions

Field

Description

PAOVF

Pulse Accumulator A Overﬂow Flag — Set when the 16-bit pulse accumulator A overﬂows from 0xFFFF to

0x0000, or when 8-bit pulse accumulator 3 (PAC3) overﬂows from 0x00FF to 0x0000.

When PACMX = 1, PAOVF bit can also be set if 8-bit pulse accumulator 3 (PAC3) reaches 0x00FF followed by

an active edge on PT3.

PAIF

Pulse Accumulator Input edge Flag — Set when the selected edge is detected at the PT7 input pin. In event

mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at

the PT7 input pin triggers PAIF.

76543210

PACNT7(15) PACNT6(14) PACNT5(13) PACNT4(12) PACNT3(11) PACNT2(10)

PACNT1(9)

PACNT0(8)

Reset

00000000

Figure 7-37. Pulse Accumulators Count Register 3 (PACN3)

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