PC312XDP512F0CFVR datasheet(369/1348 Pages) FREESCALE

369 / 1348 page

Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

369

low order PWMEx bit.In this case, the high order bytes PWMEx bits have no effect and their

corresponding PWM output lines are disabled.

While in run mode, if all eight PWM channels are disabled (PWME7–0 = 0), the prescaler counter shuts

off for power savings.

Read: Anytime

Write: Anytime

76543210

PWME7

PWME6

PWME5

PWME4

PWME3

PWME2

PWME1

PWME0

Reset

00000000

Figure 8-3. PWM Enable Register (PWME)

Table 8-1. PWME Field Descriptions

Field

Description

PWME7

Pulse Width Channel 7 Enable

0 Pulse width channel 7 is disabled.

1 Pulse width channel 7 is enabled. The pulse modulated signal becomes available at PWM output bit 7 when

its clock source begins its next cycle.

PWME6

Pulse Width Channel 6 Enable

0 Pulse width channel 6 is disabled.

1 Pulse width channel 6 is enabled. The pulse modulated signal becomes available at PWM output bit6 when

its clock source begins its next cycle. If CON67=1, then bit has no effect and PWM output line 6 is disabled.

PWME5

Pulse Width Channel 5 Enable

0 Pulse width channel 5 is disabled.

1 Pulse width channel 5 is enabled. The pulse modulated signal becomes available at PWM output bit 5 when

its clock source begins its next cycle.

PWME4

Pulse Width Channel 4 Enable

0 Pulse width channel 4 is disabled.

1 Pulse width channel 4 is enabled. The pulse modulated signal becomes available at PWM, output bit 4 when

its clock source begins its next cycle. If CON45 = 1, then bit has no effect and PWM output bit4 is disabled.

PWME3

Pulse Width Channel 3 Enable

0 Pulse width channel 3 is disabled.

1 Pulse width channel 3 is enabled. The pulse modulated signal becomes available at PWM, output bit 3 when

its clock source begins its next cycle.

PWME2

Pulse Width Channel 2 Enable

0 Pulse width channel 2 is disabled.

1 Pulse width channel 2 is enabled. The pulse modulated signal becomes available at PWM, output bit 2 when

its clock source begins its next cycle. If CON23 = 1, then bit has no effect and PWM output bit2 is disabled.

PWME1

Pulse Width Channel 1 Enable

Pulse width channel 1 is disabled.

Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when

its clock source begins its next cycle.

PWME0

Pulse Width Channel 0 Enable

0 Pulse width channel 0 is disabled.

1 Pulse width channel 0 is enabled. The pulse modulated signal becomes available at PWM, output bit 0 when

its clock source begins its next cycle. If CON01 = 1, then bit has no effect and PWM output line0 is disabled.

PC312XDP512F0CFVR Datasheet(PDF) 369 Page - Freescale Semiconductor, Inc

PC312XDP512F0CFVR Datasheet(HTML) 369 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL