PC312XDP512F0CFVR datasheet(374/1348 Pages) FREESCALE

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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

374

Freescale Semiconductor

8.3.2.7

Reserved Register (PWMTST)

This register is reserved for factory testing of the PWM module and is not available in normal modes.

Table 8-8. PWMCTL Field Descriptions

Field

Description

CON67

Concatenate Channels 6 and 7

0 Channels 6 and 7 are separate 8-bit PWMs.

1 Channels 6 and 7 are concatenated to create one 16-bit PWM channel. Channel 6 becomes the high order

byte and channel 7 becomes the low order byte. Channel 7 output pin is used as the output for this 16-bit

PWM (bit 7 of port PWMP). Channel 7 clock select control-bit determines the clock source, channel 7 polarity

bit determines the polarity, channel 7 enable bit enables the output and channel 7 center aligned enable bit

determines the output mode.

CON45

Concatenate Channels 4 and 5

0 Channels 4 and 5 are separate 8-bit PWMs.

1 Channels 4 and 5 are concatenated to create one 16-bit PWM channel. Channel 4 becomes the high order

byte and channel 5 becomes the low order byte. Channel 5 output pin is used as the output for this 16-bit

PWM (bit 5 of port PWMP). Channel 5 clock select control-bit determines the clock source, channel 5 polarity

bit determines the polarity, channel 5 enable bit enables the output and channel 5 center aligned enable bit

determines the output mode.

CON23

Concatenate Channels 2 and 3

0 Channels 2 and 3 are separate 8-bit PWMs.

1 Channels 2 and 3 are concatenated to create one 16-bit PWM channel. Channel 2 becomes the high order

byte and channel 3 becomes the low order byte. Channel 3 output pin is used as the output for this 16-bit

PWM (bit 3 of port PWMP). Channel 3 clock select control-bit determines the clock source, channel 3 polarity

bit determines the polarity, channel 3 enable bit enables the output and channel 3 center aligned enable bit

determines the output mode.

CON01

Concatenate Channels 0 and 1

0 Channels 0 and 1 are separate 8-bit PWMs.

1 Channels 0 and 1 are concatenated to create one 16-bit PWM channel. Channel 0 becomes the high order

byte and channel 1 becomes the low order byte. Channel 1 output pin is used as the output for this 16-bit

PWM (bit 1 of port PWMP). Channel 1 clock select control-bit determines the clock source, channel 1 polarity

bit determines the polarity, channel 1 enable bit enables the output and channel 1 center aligned enable bit

determines the output mode.

PSWAI

PWM Stops in Wait Mode — Enabling this bit allows for lower power consumption in wait mode by disabling

the input clock to the prescaler.

0 Allow the clock to the prescaler to continue while in wait mode.

1 Stop the input clock to the prescaler whenever the MCU is in wait mode.

PFREZ

PWM Counters Stop in Freeze Mode — In freeze mode, there is an option to disable the input clock to the

prescaler by setting the PFRZ bit in the PWMCTL register. If this bit is set, whenever the MCU is in freeze mode,

the input clock to the prescaler is disabled. This feature is useful during emulation as it allows the PWM function

to be suspended. In this way, the counters of the PWM can be stopped while in freeze mode so that once normal

program ﬂow is continued, the counters are re-enabled to simulate real-time operations. Since the registers can

still be accessed in this mode, to re-enable the prescaler clock, either disable the PFRZ bit or exit freeze mode.

0 Allow PWM to continue while in freeze mode.

1 Disable PWM input clock to the prescaler whenever the part is in freeze mode. This is useful for emulation.

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