PC312XDP512F0CFVR datasheet(380/1348 Pages) FREESCALE

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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

380

Freescale Semiconductor

8.4

Functional Description

8.4.1

PWM Clock Select

There are four available clocks: clock A, clock B, clock SA (scaled A), and clock SB (scaled B). These

four clocks are based on the bus clock.

Clock A and B can be software selected to be 1, 1/2, 1/4, 1/8,..., 1/64, 1/128 times the bus clock. Clock SA

uses clock A as an input and divides it further with a reloadable counter. Similarly, clock SB uses clock B

as an input and divides it further with a reloadable counter. The rates available for clock SA are software

selectable to be clock A divided by 2, 4, 6, 8,..., or 512 in increments of divide by 2. Similar rates are

available for clock SB. Each PWM channel has the capability of selecting one of two clocks, either the

pre-scaled clock (clock A or B) or the scaled clock (clock SA or SB).

The block diagram in Figure 8-18 shows the four different clocks and how the scaled clocks are created.

Table 8-9. PWMSDN Field Descriptions

Field

Description

PWMIF

PWM Interrupt Flag — Any change from passive to asserted (active) state or from active to passive state will

be ﬂagged by setting the PWMIF ﬂag = 1. The ﬂag is cleared by writing a logic 1 to it. Writing a 0 has no effect.

0 No change on PWM7IN input.

1 Change on PWM7IN input

PWMIE

PWM Interrupt Enable — If interrupt is enabled an interrupt to the CPU is asserted.

0 PWM interrupt is disabled.

1 PWM interrupt is enabled.

PWMRSTRT

PWM Restart — The PWM can only be restarted if the PWM channel input 7 is de-asserted. After writing a logic

1 to the PWMRSTRT bit (trigger event) the PWM channels start running after the corresponding counter passes

next “counter == 0” phase. Also, if the PWM7ENA bit is reset to 0, the PWM do not start before the counter

passes $00. The bit is always read as “0”.

PWMLVL

PWM Shutdown Output Level If active level as deﬁned by the PWM7IN input, gets asserted all enabled PWM

channels are immediately driven to the level deﬁned by PWMLVL.

0 PWM outputs are forced to 0

1 Outputs are forced to 1.

PWM7IN

PWM Channel 7 Input Status — This reﬂects the current status of the PWM7 pin.

PWM7INL

PWM Shutdown Active Input Level for Channel 7 — If the emergency shutdown feature is enabled

(PWM7ENA = 1), this bit determines the active level of the PWM7channel.

0 Active level is low

1 Active level is high

PWM7ENA

PWM Emergency Shutdown Enable — If this bit is logic 1, the pin associated with channel 7 is forced to input

and the emergency shutdown feature is enabled. All the other bits in this register are meaningful only if

PWM7ENA = 1.

0 PWM emergency feature disabled.

1 PWM emergency feature is enabled.

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