PC312XDP512F0CFVR datasheet(388/1348 Pages) FREESCALE

388 / 1348 page

Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)

MC9S12XDP512 Data Sheet, Rev. 2.21

388

Freescale Semiconductor

Figure 8-21. PWM Left Aligned Output Example Waveform

8.4.2.6

Center Aligned Outputs

For center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCAE register and the

corresponding PWM output will be center aligned.

The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is

equal to $00. The counter compares to two registers, a duty register and a period register as shown in the

block diagram in Figure 8-19. When the PWM counter matches the duty register, the output ﬂip-ﬂop

changes state, causing the PWM waveform to also change state. A match between the PWM counter and

the period register changes the counter direction from an up-count to a down-count. When the PWM

counter decrements and matches the duty register again, the output ﬂip-ﬂop changes state causing the

PWM output to also change state. When the PWM counter decrements and reaches zero, the counter

direction changes from a down-count back to an up-count and a load from the double buffer period and

duty registers to the associated registers is performed, as described in Section 8.4.2.3, “PWM Period and

Duty”. The counter counts from 0 up to the value in the period register and then back down to 0. Thus the

effective period is PWMPERx*2.

NOTE

Changing the PWM output mode from left aligned to center aligned output

(or vice versa) while channels are operating can cause irregularities in the

PWM output. It is recommended to program the output mode before

enabling the PWM channel.

Figure 8-22. PWM Center Aligned Output Waveform

Period = 400 ns

E = 100 ns

Duty Cycle = 75%

PPOLx = 0

PPOLx = 1

PWMDTYx

Period = PWMPERx*2

PWMPERx

PC312XDP512F0CFVR Datasheet(PDF) 388 Page - Freescale Semiconductor, Inc