PC312XDP512F0CFVR datasheet(456/1348 Pages) FREESCALE

456 / 1348 page

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)

MC9S12XDP512 Data Sheet, Rev. 2.21

456

Freescale Semiconductor

“MSCAN Control Register 0 (CANCTL0)”). In case of a transmission, the CPU can only read the time

stamp after the respective transmit buffer has been ﬂagged empty.

The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer

overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The

CPU can only read the time stamp registers.

Read: Anytime when TXEx ﬂag is set (see Section 10.3.2.7, “MSCAN Transmitter Flag Register

(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 10.3.2.11,

“MSCAN Transmit Buffer Selection Register (CANTBSEL)”).

Write: Unimplemented

10.4

Functional Description

10.4.1

General

This section provides a complete functional description of the MSCAN. It describes each of the features

and modes listed in the introduction.

76543210

TSR15

TSR14

TSR13

TSR12

TSR11

TSR10

TSR9

TSR8

Reset:

xxxxxxxx

Figure 10-37. Time Stamp Register — High Byte (TSRH)

76543210

TSR7

TSR6

TSR5

TSR4

TSR3

TSR2

TSR1

TSR0

Reset:

xxxxxxxx

Figure 10-38. Time Stamp Register — Low Byte (TSRL)

PC312XDP512F0CFVR Datasheet(PDF) 456 Page - Freescale Semiconductor, Inc

PC312XDP512F0CFVR Datasheet(HTML) 456 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL