PC312XDP512F0CFVR datasheet(470/1348 Pages) FREESCALE

470 / 1348 page

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)

MC9S12XDP512 Data Sheet, Rev. 2.21

470

Freescale Semiconductor

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the CPU clears the SLPRQ bit

NOTE

The CPU cannot clear the SLPRQ bit before sleep mode (SLPRQ = 1 and

SLPAK = 1) is active.

After wake-up, the MSCAN waits for 11 consecutive recessive bits to synchronize to the CAN bus. As a

consequence, if the MSCAN is woken-up by a CAN frame, this frame is not received.

The receive message buffers (RxFG and RxBG) contain messages if they were received before sleep mode

was entered. All pending actions will be executed upon wake-up; copying of RxBG into RxFG, message

aborts and message transmissions. If the MSCAN remains in bus-off state after sleep mode was exited, it

continues counting the 128 occurrences of 11 consecutive recessive bits.

Figure 10-46. Simpliﬁed State Transitions for Entering/Leaving Sleep Mode

10.4.5.5

MSCAN Initialization Mode

In initialization mode, any on-going transmission or reception is immediately aborted and synchronization

to the CAN bus is lost, potentially causing CAN protocol violations. To protect the CAN bus system from

fatal consequences of violations, the MSCAN immediately drives the TXCAN pin into a recessive state.

Wait

Idle

Tx/Rx

Message

Active

CAN Activity

CAN Activity &

Sleep

SLPRQ

StartUp

for Idle

(CAN Activity & WUPE) |

(CAN Activity & WUPE) | SLPRQ

CAN Activity

CAN Activity &

CAN Activity

SLPRQ

CAN Activity

PC312XDP512F0CFVR Datasheet(PDF) 470 Page - Freescale Semiconductor, Inc