PC312XDP512F0CFVR datasheet(484/1348 Pages) FREESCALE

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Chapter 11 Serial Communication Interface (S12SCIV5)

MC9S12XDP512 Data Sheet, Rev. 2.21

484

Freescale Semiconductor

ILT

Idle Line Type Bit — ILT determines when the receiver starts counting logic 1s as idle character bits. The

counting begins either after the start bit or after the stop bit. If the count begins after the start bit, then a string of

logic 1s preceding the stop bit may cause false recognition of an idle character. Beginning the count after the

stop bit avoids false idle character recognition, but requires properly synchronized transmissions.

0 Idle character bit count begins after start bit

1 Idle character bit count begins after stop bit

Parity Enable Bit — PE enables the parity function. When enabled, the parity function inserts a parity bit in the

most signiﬁcant bit position.

0 Parity function disabled

1 Parity function enabled

Parity Type Bit — PT determines whether the SCI generates and checks for even parity or odd parity. With even

parity, an even number of 1s clears the parity bit and an odd number of 1s sets the parity bit. With odd parity, an

odd number of 1s clears the parity bit and an even number of 1s sets the parity bit.

1 Even parity

1 Odd parity

Table 11-4. Loop Functions

LOOPS

RSRC

Function

Normal operation

Loop mode with transmitter output internally connected to receiver input

Single-wire mode with TXD pin connected to receiver input

Table 11-3. SCICR1 Field Descriptions (continued)

Field

Description

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