PC312XDP512F0CFVR datasheet(531/1348 Pages) FREESCALE

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Chapter 12 Serial Peripheral Interface (S12SPIV4)

MC9S12XDP512 Data Sheet, Rev. 2.21

Freescale Semiconductor

531

12.4.3

Transmission Formats

During an SPI transmission, data is transmitted (shifted out serially) and received (shifted in serially)

simultaneously. The serial clock (SCK) synchronizes shifting and sampling of the information on the two

serial data lines. A slave select line allows selection of an individual slave SPI device; slave devices that

are not selected do not interfere with SPI bus activities. Optionally, on a master SPI device, the slave select

line can be used to indicate multiple-master bus contention.

Figure 12-10. Master/Slave Transfer Block Diagram

12.4.3.1

Clock Phase and Polarity Controls

Using two bits in the SPI control register 1, software selects one of four combinations of serial clock phase

and polarity.

The CPOL clock polarity control bit speciﬁes an active high or low clock and has no signiﬁcant effect on

the transmission format.

The CPHA clock phase control bit selects one of two fundamentally different transmission formats.

Clock phase and polarity should be identical for the master SPI device and the communicating slave

device. In some cases, the phase and polarity are changed between transmissions to allow a master device

to communicate with peripheral slaves having different requirements.

12.4.3.2

CPHA = 0 Transfer Format

The ﬁrst edge on the SCK line is used to clock the ﬁrst data bit of the slave into the master and the ﬁrst

data bit of the master into the slave. In some peripherals, the ﬁrst bit of the slave’s data is available at the

slave’s data out pin as soon as the slave is selected. In this format, the ﬁrst SCK edge is issued a half cycle

after SS has become low.

A half SCK cycle later, the second edge appears on the SCK line. When this second edge occurs, the value

previously latched from the serial data input pin is shifted into the LSB or MSB of the shift register,

depending on LSBFE bit.

After this second edge, the next bit of the SPI master data is transmitted out of the serial data output pin of

the master to the serial input pin on the slave. This process continues for a total of 16 edges on the SCK

line, with data being latched on odd numbered edges and shifted on even numbered edges.

SHIFT REGISTER

BAUD RATE

GENERATOR

MASTER SPI

SLAVE SPI

MOSI

MISO

SCK

VDD

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