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PC312XDP512F0CFVR Datasheet(PDF) 598 Page - Freescale Semiconductor, Inc |
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PC312XDP512F0CFVR Datasheet(HTML) 598 Page - Freescale Semiconductor, Inc |
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598 / 1348 page ![]() Chapter 16 Interrupt (S12XINTV1) MC9S12XDP512 Data Sheet, Rev. 2.21 598 Freescale Semiconductor 16.1.4 Block Diagram Figure 16-1 shows a block diagram of the XINT module. Figure 16-1. XINT Block Diagram Wake Up Current RQST IVBR One Set Per Channel XGATE Interrupts XGATE Requests Interrupt Requests Interrupt Requests CPU Vector Address New IPL IPL (Up to 112 Channels) RQST DMA Request Route, PRIOLVLn Priority Level = bits from the channel configuration in the associated configuration register INT_XGPRIO = XGATE Interrupt Priority IVBR = Interrupt Vector Base IPL = Interrupt Processing Level PRIOLVL0 PRIOLVL1 PRIOLVL2 INT_XGPRIO Peripheral Vector ID To XGATE Module Priority Decoder Non I Bit Maskable Channels Wake up XGATE IRQ Channel |
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