Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

Preview PDF HTML

PC312XDP512F0CFVR Datasheet(PDF) 642 Page - Freescale Semiconductor, Inc

Part # PC312XDP512F0CFVR
Description  HCS12X Microcontrollers
PDF  1348 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PC312XDP512F0CFVR Datasheet(HTML) 642 Page - Freescale Semiconductor, Inc

Back Button PC312XDP512F0CFVR Datasheet HTML 638Page - Freescale Semiconductor, Inc PC312XDP512F0CFVR Datasheet HTML 639Page - Freescale Semiconductor, Inc PC312XDP512F0CFVR Datasheet HTML 640Page - Freescale Semiconductor, Inc PC312XDP512F0CFVR Datasheet HTML 641Page - Freescale Semiconductor, Inc PC312XDP512F0CFVR Datasheet HTML 642Page - Freescale Semiconductor, Inc PC312XDP512F0CFVR Datasheet HTML 643Page - Freescale Semiconductor, Inc PC312XDP512F0CFVR Datasheet HTML 644Page - Freescale Semiconductor, Inc PC312XDP512F0CFVR Datasheet HTML 645Page - Freescale Semiconductor, Inc PC312XDP512F0CFVR Datasheet HTML 646Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 642 / 1348 page
background image
Chapter 17 Memory Mapping Control (S12XMMCV2)
MC9S12XDP512 Data Sheet, Rev. 2.21
642
Freescale Semiconductor
17.4.4
Chip Bus Control
The MMC controls the address buses and the data buses that interface the S12X masters (CPU, BDM and
XGATE) with the rest of the system (master buses). In addition the MMC handles all CPU read data bus
swapping operations. All internal and external resources are connected to specific target buses (see
Figure 1-26).
Figure 17-26. S12X Architecture
17.4.4.1
Master Bus Prioritization
The following rules apply when prioritizing accesses over master buses:
•
The CPU has priority over the BDM, unless the BDM access is stalled for more than 128 cycles.
In the later case the CPU will be stalled after finishing the current operation and the BDM will gain
access to the bus.
•
XGATE access to PRU registers constitutes a special case. It is always granted and stalls the CPU
and BDM for its duration.
XBus2
CPU
P0
P1
P2
P3
XFLASH
XEEPROM
IPBI
EBI
XBus0
ROM/REG
BDM
IO
XBus1
RAM
XRAM
2 Kbyte Registers
S12X
S12X
XGATE
MMC
BDM
XGATE



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com