PC312XDP512F0CFVR datasheet(802/1348 Pages) FREESCALE

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Chapter 21 External Bus Interface (S12XEBIV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

804

Freescale Semiconductor

21.5.2.1

Example 2a: Emulation Single-Chip Mode

This mode is used for emulation systems in which the target application is operating in normal single-chip

mode.

Figure 21-5 shows the PRU connection with the available external bus signals in an emulator application.

Figure 21-5. Application in Emulation Single-Chip Mode

The timing diagram for this operation is shown in:

•

Figure ‘Example 2a: Emulation Single-Chip Mode — Read Followed by Write’

The associated timing numbers are given in:

•

Table ‘Example 2a: Emulation Single-Chip Mode Timing (EWAITE = 0)’

Timing considerations:

•

Signals muxed with address lines ADDRx, i.e., IVDx, IQSTATx and ACCx, have the same timing.

•

LSTRB has the same timing as R/W.

•

ECLKX2 rising edges have the same timing as ECLK edges.

•

The timing for accesses to PRU registers, which take 2 cycles to complete, is the same as the timing

for an external non-PRR access with 1 cycle of stretch as shown in example 2b.

S12X_EBI

ADDR[22:0]/IVD[15:0]

DATA[15:0]

ECLK

ECLKX2

LSTRB

R/W

ADDR[22:20]/ACC[2:0]

ADDR[19:16]/

PRR

Ports

PRU

IQSTAT[3:0]

EMULMEM

Emulator

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