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PC312XDP512F0CFVR Datasheet(PDF) 887 Page - Freescale Semiconductor, Inc |
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PC312XDP512F0CFVR Datasheet(HTML) 887 Page - Freescale Semiconductor, Inc |
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887 / 1348 page  Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 889 22.4.5 Low-Power Options 22.4.5.1 Run Mode No low-power options exist for this module in run mode. 22.4.5.2 Wait Mode No low-power options exist for this module in wait mode. 22.4.5.3 Stop Mode All clocks are stopped. There are asynchronous paths to generate interrupts from stop on port P, H, and J. 22.5 Initialization and Application Information • It is not recommended to write PORTx and DDRx in a word access. When changing the register pins from inputs to outputs, the data may have extra transitions during the write access. Initialize the port data register before enabling the outputs. PE6 GPIO GPIO GPIO TAGHI TAGHI GPIO PE5 GPIO GPIO RE TAGLO TAGLO GPIO PE4 GPIO or ECLK ECLK or GPIO ECLK or GPIO ECLK ECLK ECLK or GPIO PE3 GPIO GPIO LDS or GPIO LSTRB LSTRB LSTRB PE2 GPIO GPIO WE R/WR/WR/W PJ5 GPIO GPIO GPIO or CS2 GPIO GPIO or CS2 GPIO or CS2 PJ4 GPIO GPIO GPIO or CS0 (1) GPIO GPIO or CS0 (1) GPIO or CS0 PJ2 GPIO GPIO GPIO or CS1 GPIO GPIO or CS1 GPIO or CS1 PJ0 GPIO GPIO GPIO or CS3 GPIO GPIO or CS3 GPIO or CS3 1 Depending on ROMON bit. Refer to Device Guide, S12X_EBI section and S12X_MMC section for details. Table 22-70. Expanded Bus Pin Functions versus Operating Modes (continued) Pin Single-Chip Modes Expanded Modes Normal Single-Chip Special Single-Chip Normal Expanded Emulation Single-Chip Emulation Expanded Special Test |
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