PC312XDP512F0CFVR datasheet(903/1348 Pages) FREESCALE

903 / 1348 page

PE[7]

XCLKS1

External clock selection input during RESET

Mode

dependent3

ECLKX2

Free-running clock output at Core Clock rate (ECLK x 2)

GPIO

I/O

General-purpose I/O

PE[6]

MODB1

MODB input during RESET

TAGHI

Instruction tagging low pin

Conﬁgurable for reduced input threshold

GPIO

I/O

General-purpose I/O

PE[5]

MODA1

MODA input during RESET

Read enable signal

TAGLO

Instruction tagging low pin

Conﬁgurable for reduced input threshold

GPIO

I/O

General-purpose I/O

PE[4]

ECLK

Free-running clock output at the Bus Clock rate or

programmable divided in normal modes

GPIO

I/O

General-purpose I/O

PE[3]

EROMCTL1

EROMON bit control input during RESET

LSTRB

Low strobe bar output

LDS

Lower data strobe

GPIO

I/O

General-purpose I/O

PE[2]

R/W

Read/write output for external bus

Write enable signal

GPIO

I/O

General-purpose I/O

PE[1]

IRQ

Maskable level- or falling edge-sensitive interrupt input

GPIO

I/O

General-purpose I/O

PE[0]

XIRQ

Non-maskable level-sensitive interrupt input

GPIO

I/O

General-purpose I/O

Table 23-1. Pin Functions and Priorities (Sheet 2 of 7)

Port

Pin Name

Pin Function

and Priority

I/O

Description

Pin Function

after Reset

PC312XDP512F0CFVR Datasheet(PDF) 903 Page - Freescale Semiconductor, Inc

PC312XDP512F0CFVR Datasheet(HTML) 903 Page - Freescale Semiconductor, Inc

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