PC312XDP512F0CFVR datasheet(942/1348 Pages) FREESCALE

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Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)

MC9S12XDP512 Data Sheet, Rev. 2.21

944

Freescale Semiconductor

23.0.5.40 Port P Data Direction Register (DDRP)

Read: Anytime.

Write: Anytime.

This register configures each port P pin as either input or output.

If the associated PWM channel or SPI module is enabled this register has no effect on the pins.

The PWM forces the I/O state to be an output for each port line associated with an enabled PWM7–0

channel. Channel 7 can force the pin to input if the shutdown feature is enabled. Refer to PWM section for

details.

If SPI is enabled, the SPI determines the pin direction. Refer to SPI section for details.

The DDRP bits revert to controlling the I/O direction of a pin when the associated peripherals are disabled.

23.0.5.41 Port P Reduced Drive Register (RDRP)

Read: Anytime.

Write: Anytime.

This register configures the drive strength of each port P output pin as either full or reduced. If the port is

used as input this bit is ignored.

76543210

DDRP7

DDRP6

DDRP5

DDRP4

DDRP3

DDRP2

DDRP1

DDRP0

Reset

00000000

Figure 23-42. Port P Data Direction Register (DDRP)

Table 23-39. DDRP Field Descriptions

Field

Description

7–0

DDRP[7:0]

Data Direction Port P

0 Associated pin is conﬁgured as input.

1 Associated pin is conﬁgured as output.

Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read

on PTP or PTIP registers, when changing the DDRP register.

76543210

RDRP7

RDRP6

RDRP5

RDRP4

RDRP3

RDRP2

RDRP1

RDRP0

Reset

00000000

Figure 23-43. Port P Reduced Drive Register (RDRP)

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