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AT90PWM3 Datasheet(PDF) 130 Page - ATMEL Corporation |
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AT90PWM3 Datasheet(HTML) 130 Page - ATMEL Corporation |
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130 / 361 page  130 4317J–AVR–08/10 AT90PWM2/3/2B/3B 16.3 PSC Description Figure 16-1. Power Stage Controller 0 or 1 Block Diagram Note: n = 0, 1 The principle of the PSC is based on the use of a counter (PSC counter). This counter is able to count up and count down from and to values stored in registers according to the selected run- ning mode. The PSC is seen as two symetrical entities. One part named part A which generates the output PSCOUTn0 and the second one named part B which generates the PSCOUTn1 output. Each part A or B has its own PSC Input Module to manage selected input. OCRnRB OCRnSB OCRnRA = = = PSC Counter Waveform Generator B PSC Input Module B PSC Input Module A PSCOUTn1 PCTLn PFRCnA PSOCn ( From Analog Comparator n Ouput ) OCRnSA = PCNFn PFRCnB POM2(PSC2 only) PICRn Waveform Generator A PSCOUTn0 PSCINn Part B Part A PISELnB PISELnA PSCn Input B PSCn Input A |
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