AT90PWM3 datasheet(147/361 Pages) ATMEL

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147

4317J–AVR–08/10

AT90PWM2/3/2B/3B

If PELEVnx bit set, the significant edge of PSCn Input A or B is rising (edge modes) or the active

level is high (level modes) and vice versa for unset/falling/low

- In 2- or 4-ramp mode, PSCn Input A is taken into account only during Dead-Time0 and On-

Time0 period (respectively Dead-Time1 and On-Time1 for PSCn Input B).

- In 1-ramp-mode PSC Input A or PSC Input B act on the whole ramp.

16.8.4.3

Input Mode Operation

Thanks to 4 configuration bits (PRFM3:0), it’s possible to define the mode of the PSC input. All

Notice: All following examples are given with rising edge or high level active inputs.

Table 16-6.

PSC Input Mode Operation

PRFM3:0

Description

0000b

PSCn Input has no action on PSC output

0001b

16.9See “PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time

and Wait” on page 148.

0010b

See “PSC Input Mode 2: Stop signal, Execute Opposite Dead-Time and

Wait” on page 149.

0011b

See “PSC Input Mode 3: Stop signal, Execute Opposite while Fault

active” on page 150.

0100b

See “PSC Input Mode 4: Deactivate outputs without changing timing.” on

page 150.

0101b

See “PSC Input Mode 5: Stop signal and Insert Dead-Time” on page 151.

0110b

See “PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and

Wait.” on page 152.

0111b

See “PSC Input Mode 7: Halt PSC and Wait for Software Action” on page

152.

1000b

See “PSC Input Mode 8: Edge Retrigger PSC” on page 152.

1001b

See “PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC” on page

153.

1010b

Reserved : Do not use

1011b

1100b

1101b

1110b

See “PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and

Disactivate Output” on page 154.

1111b

Reserved : Do not use

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