AT90PWM3 datasheet(158/361 Pages) ATMEL

158 / 361 page

158

4317J–AVR–08/10

AT90PWM2/3/2B/3B

This signal can be selected between all falling or rising edge of PSCn0 or PSCn1 outputs.

In center aligned mode, OCRnRAH/L is not used, so it can be used to specified the synchroniza-

tion of the ADC. It this case, it’s minimum value is 1.

16.21 Interrupt Handling

As each PSC can be dedicated for one function, each PSC has its own interrupt system (vector

...)

List of interrupt sources:

•

Counter reload (end of On Time 1)

•

PSC Input event (active edge or at the beginning of level configured event)

•

PSC Mutual Synchronization Error

16.22 PSC Synchronization

2 or 3 PSC can be synchronized together. In this case, two waveform alignments are possible:

•

The waveforms are center aligned in the Center Aligned mode if master and slaves are all

with the same PSC period (which is the natural use).

•

The waveforms are edge aligned in the 1, 2 or 4 ramp mode

Figure 16-38. PSC Run Synchronization

If the PSCm has its PARUNn bit set, then it can start at the same time than PSCn-1.

PRUNn and PARUNn bits are located in PCTLn register. See “PSC 0 Control Register – PCTL0”

on page 164. See “PSC 1 Control Register – PCTL1” on page 165. See “PSC 2 Control Register

– PCTL2” on page 166.

PARUN0

PRUN0

Run PSC0

PSC0

PARUN1

PRUN1

Run PSC1

PSC1

PARUN2

PRUN2

Run PSC2

PSC2

SY0Out

SY0In

SY1In

SY2In

SY1Out

SY2Out

AT90PWM3 Datasheet(PDF) 158 Page - ATMEL Corporation

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