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AT90PWM3 Datasheet(PDF) 171 Page - ATMEL Corporation |
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AT90PWM3 Datasheet(HTML) 171 Page - ATMEL Corporation |
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171 / 361 page  171 4317J–AVR–08/10 AT90PWM2/3/2B/3B 16.26.4 PSC2 Interrupt Mask Register – PIM2 • Bit 5 – PSEIEn : PSC n Synchro Error Interrupt Enable When this bit is set, the PSEIn bit (if set) generate an interrupt. • Bit 4 – PEVEnB : PSC n External Event B Interrupt Enable When this bit is set, an external event which can generates a capture from Retrigger/Fault block B generates also an interrupt. • Bit 3 – PEVEnA : PSC n External Event A Interrupt Enable When this bit is set, an external event which can generates a capture from Retrigger/Fault block A generates also an interrupt. • Bit 0 – PEOPEn : PSC n End Of Cycle Interrupt Enable When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle. 16.26.5 PSC0 Interrupt Flag Register – PIFR0 16.26.6 PSC1 Interrupt Flag Register – PIFR1 16.26.7 PSC2 Interrupt Flag Register – PIFR2 • Bit 7 – POACnB : PSC n Output B Activity (not implemented on AT90PWM2/3) This bit is set by hardware each time the output PSCOUTn1 changes from 0 to 1 or from 1 to 0. Must be cleared by software by writing a one to its location. This feature is useful to detect that a PSC output doesn’t change due to a freezen external input signal. • Bit 6 – POACnA : PSC n Output A Activity (not implemented on AT90PWM2/3) This bit is set by hardware each time the output PSCOUTn0 changes from 0 to 1 or from 1 to 0. Must be cleared by software by writing a one to its location. Bit 7 654 3 2 1 0 - - PSEIE2 PEVE2B PEVE2A - - PEOPE2 PIM2 Read/Write R R R/W R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 654 3 2 1 0 POAC0B POAC0A PSEI0 PEV0B PEV0A PRN01 PRN00 PEOP2 PIFR0 Read/Write R R R/W R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 654 3 2 1 0 POAC1B POAC1A PSEI1 PEV1B PEV1A PRN11 PRN10 PEOP1 PIFR1 Read/Write R R R/W R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 654 3 2 1 0 POAC2B POAC2A PSEI2 PEV2B PEV2A PRN21 PRN20 PEOP2 PIFR2 Read/Write R R R/W R/W R/W R R R/W Initial Value 0 0 0 0 0 0 0 0 |
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