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C8051F50X Datasheet(PDF) 52 Page - Silicon Laboratories

Part # C8051F50X
Description  Mixed Signal ISP Flash MCU Family
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F50X Datasheet(HTML) 52 Page - Silicon Laboratories

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C8051F50x-F51x
52
Rev. 1.1
6. 12-Bit ADC (ADC0)
The ADC0 on the C8051F50x-F51x consists of an analog multiplexer (AMUX0) with 35/28 total input
selections and a 200 ksps, 12-bit successive-approximation-register (SAR) ADC with integrated track-and-
hold, programmable window detector, programmable attenuation (1:2), and hardware accumulator. The
ADC0 subsystem has a special Burst Mode which can automatically enable ADC0, capture and accumu-
late samples, then place ADC0 in a low power shutdown mode without CPU intervention. The AMUX0,
data conversion modes, and window detector are all configurable under software control via the Special
Function Registers shows in Figure 6.1. ADC0 inputs are single-ended and may be configured to measure
P0.0-P3.7, the Temperature Sensor output, VDD, or GND with respect to GND. The voltage reference for
ADC0 is selected as described in Section “7. Temperature Sensor” on page 72. ADC0 is enabled when the
AD0EN bit in the ADC0 Control register (ADC0CN) is set to logic 1, or when performing conversions in
Burst Mode. ADC0 is in low power shutdown when AD0EN is logic 0 and no Burst Mode conversions are
taking place.
Figure 6.1. ADC0 Functional Block Diagram
ADC0CN
Start
Conversion
VDD
35-to-1
AMUX0
VDD
P0.0
P0.7
P1.0
P1.7
ADC0MX
GND
Temp Sensor
ADC0TK
Burst Mode
Logic
Start
Conversion
Burst Mode
Oscillator
25 MHz Max
SYSCLK
*Available on 48-pin and
40-pin packages
00
AD0BUSY (W)
10
CNVSTR Input
Timer 2 Overflow
11
01
Timer 1 Overflow
12-Bit
SAR
ADC
32
ADC0LTH
AD0WINT
ADC0LTL
ADC0GTH ADC0GTL
ADC0CF
Accumulator
Window
Compare
Logic
Selectable
Gain
P2.0
P2.7
P3.0
P3.7*
P3.1*
ADC0GNL
ADC0GNH
ADC0GNA


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