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C8051F50X Datasheet(PDF) 73 Page - Silicon Laboratories |
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C8051F50X Datasheet(HTML) 73 Page - Silicon Laboratories |
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73 / 312 page  Rev. 1.1 73 C8051F50x-F51x 8. Voltage Reference The Voltage reference multiplexer on the C8051F50x-F51x devices is configurable to use an externally connected voltage reference, the on-chip reference voltage generator routed to the VREF pin, or the VDD power supply voltage (see Figure 8.1). The REFSL bit in the Reference Control register (REF0CN, SFR Definition 8.1) selects the reference source for the ADC. For an external source or the on-chip reference, REFSL should be set to 0 to select the VREF pin. To use VDD as the reference source, REFSL should be set to 1. The BIASE bit enables the internal voltage bias generator, which is used by the ADC, Temperature Sensor, and internal oscillator. This bias is automatically enabled when any peripheral which requires it is enabled, and it does not need to be enabled manually. The bias generator may be enabled manually by writing a 1 to the BIASE bit in register REF0CN. The electrical specifications for the voltage reference circuit are given in Table 5.11. The on-chip voltage reference circuit consists of a temperature stable bandgap voltage reference genera- tor and a gain-of-two output buffer amplifier. The output voltage is selectable between 1.5 V and 2.25 V. The on-chip voltage reference can be driven on the VREF pin by setting the REFBE bit in register REF0CN to a 1. The maximum load seen by the VREF pin must be less than 200 µA to GND. Bypass capacitors of 0.1 µF and 4.7 µF are recommended from the VREF pin to GND. If the on-chip reference is not used, the REFBE bit should be cleared to 0. Electrical specifications for the on-chip voltage reference are given in Table 5.11. Important Note about the VREF Pin: When using either an external voltage reference or the on-chip ref- erence circuitry, the VREF pin should be configured as an analog pin and skipped by the Digital Crossbar. Refer to Section “20. Port Input/Output” on page 177 for the location of the VREF pin, as well as details of how to configure the pin in analog mode and to be skipped by the crossbar. Figure 8.1. Voltage Reference Functional Block Diagram VREF (to ADC) To Analog Mux VDD VREF R1 VDD External Voltage Reference Circuit GND Temp Sensor EN Bias Generator To ADC, Internal Oscillators EN IOSCE N 0 1 REF0CN REFBE Internal Reference EN Recommended Bypass Capacitors + 4.7 F0.1F |
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