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C8051F50X Datasheet(PDF) 75 Page - Silicon Laboratories |
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C8051F50X Datasheet(HTML) 75 Page - Silicon Laboratories |
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75 / 312 page  Rev. 1.1 75 C8051F50x-F51x 9. Comparators The C8051F50x-F51x devices include two on-chip programmable voltage Comparators. A block diagram of the comparators is shown in Figure 9.1, where “n” is the comparator number (0 or 1). The two Compara- tors operate identically except that Comparator0 can also be used a reset source. For input selection details, refer to SFR Definition 9.5 and SFR Definition 9.6. Each Comparator offers programmable response time and hysteresis, an analog input multiplexer, and two outputs that are optionally available at the Port pins: a synchronous “latched” output (CP0, CP1), or an asynchronous “raw” output (CP0A, CP1A). The asynchronous signal is available even when the system clock is not active. This allows the Comparators to operate and generate an output with the device in STOP mode. When assigned to a Port pin, the Comparator outputs may be configured as open drain or push-pull (see Section “20.4. Port I/O Initialization” on page 182). Comparator0 may also be used as a reset source (see Section “17.5. Comparator0 Reset” on page 145). The Comparator0 inputs are selected in the CPT0MX register (SFR Definition 9.5). The CMX0P1-CMX0P0 bits select the Comparator0 positive input; the CMX0N1-CMX0N0 bits select the Comparator0 negative input. The Comparator1 inputs are selected in the CPT1MX register (SFR Definition 9.6). The CMX1P1- CMX1P0 bits select the Comparator1 positive input; the CMX1N1-CMX1N0 bits select the Comparator1 negative input. Important Note About Comparator Inputs: The Port pins selected as Comparator inputs should be con- figured as analog inputs in their associated Port configuration register, and configured to be skipped by the Crossbar (for details on Port configuration, see Section “20.1. Port I/O Modes of Operation” on page 178). Figure 9.1. Comparator Functional Block Diagram VIO Reset Decision Tree + - Crossbar Q Q SET CLR D Q Q SET CLR D (SYNCHRONIZER) GND CPn + CPn - CPTnMD CPn CPnA CPn Interrupt 0 1 0 1 CPnRIF CPnFIF 0 1 CPnEN 0 1 EA Comparator Input Mux CPTnCN |
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