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C8051F50X Datasheet(PDF) 86 Page - Silicon Laboratories |
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C8051F50X Datasheet(HTML) 86 Page - Silicon Laboratories |
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86 / 312 page  C8051F50x-F51x 86 Rev. 1.1 11. CIP-51 Microcontroller The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft- ware. The MCU family has a superset of all the peripherals included with a standard 8051. The CIP-51 also includes on-chip debug hardware (see description in Section 28), and interfaces directly with the ana- log and digital subsystems providing a complete data acquisition or control-system solution in a single inte- grated circuit. The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability (see Figure 11.1 for a block diagram). The CIP-51 includes the following features: Fully Compatible with MCS-51 Instruction Set 50 MIPS Peak Throughput with 50 MHz Clock 0 to 50 MHz Clock Frequency Extended Interrupt Handler Reset Input Power Management Modes On-chip Debug Logic Program and Data Memory Security 11.1. Performance The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan- dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51 core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more than eight system clock cycles. |
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