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C8051F50X Datasheet(PDF) 18 Page - Silicon Laboratories |
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C8051F50X Datasheet(HTML) 18 Page - Silicon Laboratories |
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18 / 312 page  C8051F50x-F51x 18 Rev. 1.1 Figure 1.2. C8051F508/9-F510/1 Block Diagram Digital Peripherals *On ‘F508-F510 devices UART0 Timers 0, 1, 2, 3 6 channel PCA/WDT LIN 2.1 Priority Crossbar Decoder P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6/ P0.7 Crossbar Control Port I/O Configuration SFR Bus P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 SPI Debug / Programming Hardware Power On Reset Reset C2D C2CK/RST P1.6 P1.7 Analog Peripherals Comparator 0 + - 12-bit 200ksps ADC A M U X VREF VDD VDD VREF GND CP0, CP0A Voltage Reference VREF System Clock Setup External Oscillator XTAL1 CIP-51 8051 Controller Core up to 64 kB Byte Flash Program Memory 256 Byte RAM Port 0 Drivers Port 1 Drivers Voltage Regulator (LDO) GND VREGIN VDD XTAL2 VIO P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Port 2 Drivers Port 3 Drivers P4.0 / C2D Port 4 Driver Temp Sensor P0 – P3 Comparator 1 + - CP1, CP1A CAN 2.0B GNDA VDDA Clock Multiplier Internal Oscillator External Memory Interface 4 kB XRAM I2C |
Similar Part No. - C8051F50X |
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Similar Description - C8051F50X |
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