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C8051F50X Datasheet(PDF) 20 Page - Silicon Laboratories |
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C8051F50X Datasheet(HTML) 20 Page - Silicon Laboratories |
20 / 312 page C8051F50x-F51x 20 Rev. 1.1 2. Ordering Information The following features are common to all devices in this family: 50 MHz system clock and 50 MIPS throughput (peak) 4352 bytes of RAM (256 internal bytes and 4096 XRAM bytes) SMBus/I2C, Enhanced SPI, Enhanced UART Four Timers Six Programmable Counter Array channels Internal 24 MHz oscillator that is accurate to within ±0.5% across operating temperature and voltage. Internal Voltage Regulator 12-bit, 200 ksps ADC Internal Voltage Reference and Temperature Sensor Two Analog Comparators Table 2.1 shows the feature that differentiate the devices in this family. |
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