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C8051F50X Datasheet(PDF) 22 Page - Silicon Laboratories |
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C8051F50X Datasheet(HTML) 22 Page - Silicon Laboratories |
22 / 312 page C8051F50x-F51x 22 Rev. 1.1 3. Pin Definitions Table 3.1. Pin Definitions for the C8051F50x-F51x Name Pin ‘F500/1/4/5 (48-pin) Pin F508/9- F510/1 (40-pin) Pin ‘F502/3/6/7 (32-pin) Type Description VDD 4 4 4 Digital Supply Voltage. Must be connected. GND 6 6 6 Digital Ground. Must be connected. VDDA 5 5 5 Analog Supply Voltage. Must be connected. GNDA 7 7 7 Analog Ground. Must be connected. VREGIN 3 3 3 Voltage Regulator Input VIO 2 2 2 Port I/O Supply Voltage. Must be connected. RST/ C2CK 12 10 10 D I/O D I/O Device Reset. Open-drain output of internal POR or VDD Monitor. An external source can initiate a system reset by driving this pin low. Clock signal for the C2 Debug Interface. C2D 11 — — D I/O Bi-directional data signal for the C2 Debug Interface. P4.0/ C2D — 9 — D I/O or A In D I/O Port 4.0. See SFR Definition 20.29 for a description. Bi-directional data signal for the C2 Debug Interface. P3.0/ C2D — 9 D I/O or A In D I/O Port 3.0. See SFR Definition 20.24 for a description. Bi-directional data signal for the C2 Debug Interface. P0.0 8 8 8 D I/O or A In Port 0.0. See SFR Definition 20.12 for a description. P0.1 1 1 1 D I/O or A In Port 0.1 P0.2 48 40 32 D I/O or A In Port 0.2 P0.3 47 39 31 D I/O or A In Port 0.3 P0.4 46 38 30 D I/O or A In Port 0.4 P0.5 45 37 29 D I/O or A In Port 0.5 |
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