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C8051F50X Datasheet(PDF) 31 Page - Silicon Laboratories |
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C8051F50X Datasheet(HTML) 31 Page - Silicon Laboratories |
31 / 312 page Rev. 1.1 31 C8051F50x-F51x Figure 4.2. QFP-48 Landing Diagram Table 4.2. QFP-48 Landing Diagram Dimensions Dimension Min Max Dimension Min Max C1 8.30 8.40 X1 0.20 0.30 C2 8.30 8.40 Y1 1.40 1.50 E 0.50 BSC Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design 4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. The stencil thickness should be 0.125mm (5 mils). 6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. Card Assembly 7. A No-Clean, Type-3 solder paste is recommended. 8. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. |
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