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C8051F50X Datasheet(PDF) 38 Page - Silicon Laboratories |
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C8051F50X Datasheet(HTML) 38 Page - Silicon Laboratories |
38 / 312 page C8051F50x-F51x 38 Rev. 1.1 4.5. QFN-32 Package Specifications Figure 4.9. QFN-32 Package Drawing Table 4.9. QFN-32 Package Dimensions Dimension Min Typ Max Dimension Min Typ Max A 0.80 0.9 1.00 E2 3.20 3.30 3.40 A1 0.00 0.02 0.05 L 0.30 0.40 0.50 b 0.18 0.25 0.30 L1 0.00 — 0.15 D 5.00 BSC. aaa — — 0.15 D2 3.20 3.30 3.40 bbb — — 0.15 e 0.50 BSC. ddd — — 0.05 E 5.00 BSC. eee — — 0.08 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220, variation VGGD except for custom features D2, E2, and L which are toleranced per supplier designation. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. |
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