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C8051F50X Datasheet(PDF) 44 Page - Silicon Laboratories

Part # C8051F50X
Description  Mixed Signal ISP Flash MCU Family
Download  312 Pages
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Manufacturer  SILABS [Silicon Laboratories]
Direct Link  http://www.silabs.com
Logo SILABS - Silicon Laboratories

C8051F50X Datasheet(HTML) 44 Page - Silicon Laboratories

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C8051F50x-F51x
44
Rev. 1.1
Figure 5.1. Minimum VDD Monitor Threshold vs. System Clock Frequency
Note:
With system clock frequencies greater than 25 MHz, the VDD monitor level should be set to the high threshold
(VDMLVL = 1b in SFR VDM0CN) to prevent undefined CPU operation. The high threshold should only be used
with an external regulator powering VDD directly. See Figure 10.2 on page 85 for the recommended power
supply connections.


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