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C8051F503-IQ Datasheet(PDF) 9 Page - Silicon Laboratories |
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C8051F503-IQ Datasheet(HTML) 9 Page - Silicon Laboratories |
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9 / 312 page  Rev. 1.1 9 C8051F50x-F51x Figure 13.4. SFR Page Stack Upon PCA Interrupt Occurring During a CAN0 ISR 104 Figure 13.5. SFR Page Stack Upon Return From PCA Interrupt .......................... 105 Figure 13.6. SFR Page Stack Upon Return From CAN0 Interrupt ........................ 106 Figure 15.1. Flash Program Memory Map ............................................................. 131 Figure 17.1. Reset Sources ................................................................................... 141 Figure 17.2. Power-On and VDD Monitor Reset Timing ....................................... 142 Figure 18.1. Multiplexed Configuration Example ................................................... 153 Figure 18.2. Non-multiplexed Configuration Example ........................................... 154 Figure 18.3. EMIF Operating Modes ..................................................................... 155 Figure 18.4. Non-multiplexed 16-bit MOVX Timing ............................................... 158 Figure 18.5. Non-multiplexed 8-bit MOVX without Bank Select Timing ................ 159 Figure 18.6. Non-multiplexed 8-bit MOVX with Bank Select Timing ..................... 160 Figure 18.7. Multiplexed 16-bit MOVX Timing ....................................................... 161 Figure 18.8. Multiplexed 8-bit MOVX without Bank Select Timing ........................ 162 Figure 18.9. Multiplexed 8-bit MOVX with Bank Select Timing ............................. 163 Figure 19.1. Oscillator Options .............................................................................. 165 Figure 19.2. Example Clock Multiplier Output ....................................................... 170 Figure 19.3. External 32.768 kHz Quartz Crystal Oscillator Connection Diagram 175 Figure 20.1. Port I/O Functional Block Diagram .................................................... 177 Figure 20.2. Port I/O Cell Block Diagram .............................................................. 178 Figure 20.3. Peripheral Availability on Port I/O Pins .............................................. 181 Figure 20.4. Crossbar Priority Decoder in Example Configuration ........................ 182 Figure 21.1. LIN Block Diagram ............................................................................ 201 Figure 22.1. Typical CAN Bus Configuration ......................................................... 218 Figure 22.2. CAN Controller Diagram .................................................................... 219 Figure 22.3. Four segments of a CAN Bit .............................................................. 221 Figure 23.1. SMBus Block Diagram ...................................................................... 226 Figure 23.2. Typical SMBus Configuration ............................................................ 227 Figure 23.3. SMBus Transaction ........................................................................... 228 Figure 23.4. Typical SMBus SCL Generation ........................................................ 230 Figure 23.5. Typical Master Write Sequence ........................................................ 237 Figure 23.6. Typical Master Read Sequence ........................................................ 238 Figure 23.7. Typical Slave Write Sequence .......................................................... 239 Figure 23.8. Typical Slave Read Sequence .......................................................... 240 Figure 24.1. UART0 Block Diagram ...................................................................... 243 Figure 24.2. UART0 Timing Without Parity or Extra Bit ......................................... 245 Figure 24.3. UART0 Timing With Parity ................................................................ 245 Figure 24.4. UART0 Timing With Extra Bit ............................................................ 245 Figure 24.5. Typical UART Interconnect Diagram ................................................. 246 Figure 24.6. UART Multi-Processor Mode Interconnect Diagram ......................... 247 Figure 25.1. SPI Block Diagram ............................................................................ 252 Figure 25.2. Multiple-Master Mode Connection Diagram ...................................... 255 Figure 25.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram .......................................................................... 255 |
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