Document #: 38-05486 Rev. *H

Page 7 of 16

Switching Characteristics

Over the Operating Range [11, 12]

Parameter

Description

45 ns (Industrial)

55 ns (Automotive)

Unit

Min

Max

Min

Max

Read Cycle

Read cycle time

45

–

55

–

ns

Address to data valid

–

45

–

55

ns

Data hold from address change

10

–

10

–

ns

CE LOW to data valid

–

45

–

55

ns

OE LOW to data valid

–

22

–

25

ns

OE LOW to Low Z [13]

5

–

5

–

ns

OE HIGH to High Z [13, 14]

–

18

–

20

ns

CE LOW to Low Z [13]

10

–

10

–

ns

CE HIGH to High Z [13, 14]

–

18

–

20

ns

CE LOW to power up

0

–

0

–

ns

CE HIGH to power down

–

45

–

55

ns

BHE / BLE LOW to data valid

–

22

–

25

ns

BHE / BLE LOW to Low Z [13]

5

–

5

–

ns

BHE / BLE HIGH to High Z [13, 14]

–

18

–

20

ns

Write Cycle [15]

Write cycle time

45

–

55

–

ns

CE LOW to write end

35

–

40

–

ns

Address setup to write end

35

–

40

–

ns

Address hold from write end

0

–

0

–

ns

Address setup to write start

0

–

0

–

ns

WE pulse width

35

–

40

–

ns

BHE / BLE pulse width

35

–

40

–

ns

Data setup to write end

25

–

25

–

ns

Data hold from write end

0

–

0

–

ns

WE LOW to High Z [13, 14]

–

18

–

20

ns

WE HIGH to Low Z [13]

10

–

10

–

ns

Notes

12. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.

signals can terminate a write by going inactive. The data input setup and hold timing must refer to the edge of signal that terminates write.