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AT42QT1111-MU Datasheet(PDF) 25 Page - ATMEL Corporation |
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AT42QT1111-MU Datasheet(HTML) 25 Page - ATMEL Corporation |
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25 / 50 page  25 9571A–AT42–02/10 AT42QT1111-MU/AT42QT1111-AU 6.3 All Keys (0xC1) Returns a 2-byte bit-field report indicating the detection status of all 11 keys. KEY_n: 0 = key n out of detect, 1 = key n in detect (where n is 0–10). 6.4 Device Status (0xC2) This command returns a 1-byte bit-field report indicating the overall status of the QT1111. Bits 7 is always 1; the other bits are as follows: DETECT: 0 = no key in detect, 1 = at least 1 key in detect. CYCLE: 0 = cycle time is good, 1 = cycle time over-run. A cycle time over-run occurs when it takes longer to measure and process all the keys than the assigned cycle time. ERROR: 0 = no key in error state, 1 = at least 1 key in error. CHANGE: 0 = CHANGE pin is asserted, 1 = CHANGE pin is floating. EEPROM: 0 = EEPROM is good, 1 = EEPROM has an error. If there are no settings stored in EEPROM, the EEPROM error bit is set and a zero EEPROM CRC is returned. RESET: set to 1 after power-on or reset, cleared when “Device Status” is read. GUARD: 0 = guard channel is not in detect, 1 = guard channel is active or in detect. This bit will be zero if the guard channel is not enabled. 6.5 EEPROM CRC (0xC3) This command returns a 1-byte CRC checksum for the setup data in EEPROM. 6.6 RAM CRC (0xC4) This command returns a 1-byte CRC checksum for the setup data in RAM. Table 6-3. Send All Keys Report Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 0 KEY_10 KEY_9 KEY_8 Byte 1 KEY_7 KEY_6 KEY_5 KEY_4 KEY_3 KEY_2 KEY_1 KEY_0 Table 6-4. Device Status Report Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Byte 0 1 DETECT CYCLE ERROR CHANGE EEPROM RESET GUARD |
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