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AT42QT1111-MU Datasheet(PDF) 30 Page - ATMEL Corporation |
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AT42QT1111-MU Datasheet(HTML) 30 Page - ATMEL Corporation |
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30 / 50 page  30 9571A–AT42–02/10 AT42QT1111-MU/AT42QT1111-AU REPEAT_TIME: selects the “repeat” time when “Timed” is selected as the trigger to start key acquisition. The number entered is a multiple of 16 ms. If “0” is entered, the device will operate in a continuous “free run” mode; that is, the QT1111 will not sleep after its cycle is completed but will begin the next key acquisition cycle immediately. Default KEY_AC value: 1 (timed) Default MODE value: 0 (7-key mode) Default SIGNAL value: 1 (parallel) Default SYNC value: 1 (edge) Default REPEAT_TIME value: 2 (32 ms cycle) 7.5 Address 1: Guard Key/Comms Options GUARD_KEY: specifies the key (0 to 10) to be used as a guard channel (see Section 2.3 on page 7) . GD_EN: enables the use of a guard key; 0 = disable, 1 = enable. SPI_EN: enables the Quick SPI interface; 0 = disable, 1 = enable (see Table 7-4). See Section 4.1.6 on page 16 for details of the Quick SPI Mode report. To exit this mode (and clear the “SPI_EN” bit), the command “0x36” should be sent. To save the settings to EEPROM and make Quick SPI mode active on startup, send the “Store to EEPROM” command (0x0A). Any other data sent is ignored in Quick SPI mode. CHG: the CHANGE pin mode (see Section 4.5 on page 17): 0 = “Data” mode. In this mode the “Change” pin is asserted to indicate unread data. 1 = “Touch” mode. In this mode the “Change” pin is asserted when a key is being touched or is in detect. CRC: enables or disables CRC; 0 = disable, 1 = enable. When this option is enabled, each data exchange must have a CRC byte appended. When report or setup data is being returned by the QT1111, a 1-byte checksum is returned. The host should confirm that this checksum is correct and, if not, should request the report again. Table 7-3. Guard Key/Comms Options Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 GUARD_KEY GD_EN SPI_EN CHG CRC Table 7-4. Status Information Bytes Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 Counter 1 Key 3 status Key 2 status Key 1 status Key 0 status 2 Key 7 status Key 6 status Key 5 status Key 4 status 3 Reserved Key 10 status Key 9 status Key 8 status 4 Key 3 error Key 2 error Key 1 error Key 0 error 5 Key 7 error Key 6 error Key 5 error Key 4 error 6 Reserved Key 10 error Key 9 error Key 8 error |
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